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-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:39:57 09/26/2013 
-- Design Name: 
-- Module Name:    op_counter - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity op_counter is
	port(	clock : in STD_LOGIC;
			reset : in STD_LOGIC;
			max : in STD_LOGIC_VECTOR(5 downto 0);
			count : out STD_LOGIC_VECTOR(5 downto 0));
end op_counter;

architecture Behavioral of op_counter is
	component d_flip_flop is
		 Port ( 	clock : in  STD_LOGIC;
					reset : in  STD_LOGIC;
					hold : in STD_LOGIC;
					input : in  STD_LOGIC;
					output : out  STD_LOGIC);
	end component;
	
	signal hold : STD_LOGIC := '0';
	signal f0f1 : STD_LOGIC;
	signal f0f1f2 : STD_LOGIC;
	signal f0f1f2f3 : STD_LOGIC;
	signal f0f1f2f3f4 : STD_LOGIC;
	signal countIntermediate : STD_LOGIC_VECTOR(5 downto 0);
	
begin
	flipFlop0 : d_flip_flop port map(clock, reset, hold, '1', countIntermediate(0));
	flipFlop1 : d_flip_flop port map(clock, reset, hold, countIntermediate(0),countIntermediate(1));
	flipFlop2 : d_flip_flop port map(clock, reset, hold, f0f1, countIntermediate(2));
	flipFlop3 : d_flip_flop port map(clock, reset, hold, f0f1f2, countIntermediate(3));
	flipFlop4 : d_flip_flop port map(clock, reset, hold, f0f1f2f3, countIntermediate(4));
	flipFlop5 : d_flip_flop port map(clock, reset, hold, f0f1f2f3f4, countIntermediate(5));
	
	f0f1 <= countIntermediate(0) and countIntermediate(1);
	f0f1f2 <= f0f1 and countIntermediate(2);
	f0f1f2f3 <= f0f1f2 and countIntermediate(3);
	f0f1f2f3f4 <= f0f1f2f3 and countIntermediate(4);
	count <= countIntermediate;
	
	hold <= 	'1' when countIntermediate = max else
				'0';
	
end Behavioral;

